Design of logic circuits with wired-logic utilizing transduction method

Wired-Logic is especially useful when designing fan-in restricted logic circuits which are implemented with bipolar and MOS transistors. However, there are few papers about logic design with Wired-Logic except the paper of the authors. In this paper, a method which reduces the levels of circuits by utilizing Wired-Logic is presented. The method restricts the number of fan-ins of a gate utilizing Wired-Logic. It e ciently utilizes Wired-Logic by transforming circuits using Transduction Method which is an optimization method. For the combination of NOR gates and Wired-OR gates which is especially important, an algorithm to utilize WiredOR gates for the fan-in restriction is also presented. By performing experiments on 3-level NOR circuits, the proposed method is compared with Generalized Serial Duplication which is an e cient Serial Duplication. The levels of most circuits are reduced by utilizing Wired-OR gates, which shows the e ciency of Wired-Logic. The proposed method can be modi ed to use the cost function as the connection length which is more important than the levels of circuits. key word : logic design, Transduction Method, Wired-Logic, fan-in restriction